Implementing custom risc-v extensions

IDA General
1

In risc-v world, it is common that cores implement vendor-specific custom instructions (or CSRs, or other tweaks to the basic architecture).

Is it possible for end-users to extend ida’s existing risc-v support such that the decompiler is also aware of the new instructions?

Specifically I’m currently interested in andes v5 extensions, however this is a general question as the functionality would be better to have as end-user implementable, since there are a huge number of possible extensions/configurations, and it grows rapidly.

I used to be more active ida user - afaik this functionality does not exist. however maybe that changed recently-ish?

2

Hi @shawn,

The good news is that we have a way to do that. The decompiler SDK includes a filter microcode_filter_t, which allows you to teach the decompiler unsupported instructions of an otherwise supported architecture.

As a great real-world example, you may take a look at this project made by the CTF team: GitHub - 0rganizers/nmips: nanoMIPS IDA plugin
which extended our MIPS decompiler to nanoMIPS back when we didn’t support it natively.

Hope it helps with your implementation!

1 Like
3

I wound up doing this in ghidra as it’s a lot more straightforward.
however, I see ida is adding andes support in 9.3 (nds32), so maybe you are interested in some of the resources I’ve posted in this thread: Implementing indirect instruction execution in processor plugin · NationalSecurityAgency/ghidra · Discussion #6612 · GitHub

It includes instruction encodings for undocumented andes v5 (riscv) instructions, and some binaries for v3/v5 in other posts ( Implementing indirect instruction execution in processor plugin · NationalSecurityAgency/ghidra · Discussion #6612 · GitHub )